The standard method of forming an integrated circuit consists basically of defining a pattern lithographically in a photosensitive material and then removing or depositing a layer of the integrated circuit according to the pattern.
The lithography is performed in a composite tool that combines the steps of applying the photoresist, baking it, and developing it in a first unit and the step of exposing the resist to photons in a second unit. The two units are combined in a common envelope, referred to as a combined tool, so that transfer between the units does not expose the wafer to the ambient atmosphere in the clean room of the fab.
The process requires a deposition tool, typically using a type of chemical vapor deposition to deposit the unpatterned layer material and an ashing tool to remove residues of the photoresist, for a total of three tools.
A clean room has a highly controlled ambient atmosphere that is nevertheless more contaminated with foreign matter than the atmosphere within the composite lithography tool.
A simplified list of the steps on the material deposition and pattern process is set forth in Table I.
TABLE IBlanket material depositionResist coatSoftbake ResistWafer transfer to StepperPattern ExposureWafer transfer from stepperHardbake ResistDevelop ResistEtch Removal of Deposited MaterialWafer Transfer to Ashing ToolAsh ResistPost Removal Clean
In many integrated circuits using advanced technology, this sequence may be repeated up to 20 times. Integrated circuits using embedded DRAM modules require even more steps.
The manufacture of integrated circuits is a highly competitive field and manufacturers are constantly seeking to reduce costs.
The art could benefit from a process for forming a patterned layer that requires fewer steps and/or fewer tools than the current process.